1. Field of the Invention
The present invention relates to an automatic adjusting method and circuit.
2. Description of the Related Art
In one approach used for an automatic adjustment for a video sampling clock phase in a liquid crystal display device, phase control data is transmitted from a CPU, and then the CPU receives video detection data detected from an image sampled and displayed at a set phase value. This processing is repeated while the value is varied to determine an optimal phase value based on the received video detection data. The automatic phase adjustment requires a wait time which is the sum of a period taken for transmitting phase setting data, and period taken for displaying one screen of sampled image with a set phase value.
A prior art example of automatic phase adjustment will now be described with reference to FIGS. 1, 2 and 3.
FIG. 1 illustrates an exemplary circuit configuration for performing a conventional automatic phase adjustment; FIG. 2 illustrates an exemplary flow chart of the conventional automatic phase adjustment; and FIG. 3 illustrates an exemplary timing chart for the conventional automatic phase adjustment.
The illustrated circuit comprises A/D converter 101 for sampling analog video input signal V101 generated by a personal computer or the like with sampling pulse S107 to convert signal V101 to digital video signal V102; digital video signal processor 102 for performing a color correction and scaling processing on digital video signal V102; display unit 103 for displaying processed digital video signal V103; clock pulse generator 105 for generating clock pulse S105, with which an analog video signal is sampled from horizontal synchronization signal S101; phase controller 106 for controlling the phase of clock pulse S105; CPU 104 for controlling respective peripheral circuits, such as supplying clock pulse frequency control data S103 and phase control data S104; video detector 108 for calculating video detection data S106 from digital video signal V102 for use in an automatic adjustment, and for supplying video detection data S106 when triggered by vertical synchronization signal S102; and video detection data memory 109 for holding video detection data S106 and supplying video detection data S106 in response to a read operation of CPU 104.
Now, description will be made on the operation of the conventional automatic phase adjusting circuit. Assume in the following description that phase shift amount CLK_DLY has maximum value DLY_MAX, and the phase shifted by DLY_MAX+1 corresponds to a full one-cycle shift of the phase.
At step F701, phase shift amount CLK_DLY is set to zero. CPU 104 supplies phase controller 106 with phase control data S104 (CLK_DLY=0).
At step F702, CPU 104 waits for an interrupt of vertical synchronization signal S102 which serves as a trigger pulse. The flow proceeds to step F703 when an interrupt is generated.
At step F703, CPU 104 waits for an interrupt of vertical synchronization signal S102 which serves as a trigger pulse. The flow proceeds to step F704 when an interrupt is generated.
At step F704, CPU 104 confirms whether phase shift amount CLK_DLY has reached maximum value DLY_MAX. When the phase shift amount has reached the maximum value, the flow proceeds to step F707. Conversely, when the phase shift amount has not reached the maximum value, the flow proceeds to step F705.
At step F705, CPU 104 reads from video detection data memory 109 video detection data S106 (VIDEO_DATA(0)) when CLK_DLY=0. Read video detection data S106 is held in RAM, not shown, in CPU 104 as optimal phase determination data at each phase set value.
At step F706, CPU 104 supplies phase controller 106 with phase control data S104 (CLK_DLY=CLK_DLY+1=1). As step F706 terminates, the flow returns again to step F702. This loop of processing is repeated until the condition at step F704 is satisfied.
At step F707, CPU 104 reads from video detection data memory 109 video detection data S106 (VIDEO_DATA(DLY_MAX)) when CLK_DLY=DLY_MAX. At this time, CPU 104 acquires optimal phase determination data at each of phase set values from CLK_DLY=0 to DLY_MAX.
At step F708, CPU 104 analyzes the acquired optimal phase determination data at the respective phase set values to calculate an optimal phase value.
At step F709, CPU 104 supplies the calculated optimal phase value to phase controller 106 as phase control data S104. Phase controller 106 controls a phase delay amount for clock pulse S105 in accordance with phase control data S104, and supplies A/D converter 101 with phase-controlled clock pulse S105 as sampling pulse S107. Subsequently, the processing is performed in a manner similar to that in a normal display state to display a video sampled at the optimal phase on display unit 103.
A wait time required for the sequence of processing is calculated as (vertical synchronization period×(DLY_MAX+1)×2)).
The prior art example described above ensures a period for displaying one screen of image sampled at a set phase value by first setting phase shift amount CLK_DLY to zero and waiting for two interrupts of vertical synchronization signal S102 which serves as a trigger pulse, thereby giving rise to a problem of failing to reduce the wait time and requiring an excessive amount of time for the automatic adjustment.
In an approach used in the automatic adjustment for the phase of a video sampling clock in a liquid crystal display device for displaying a sampled analog video output signal generated by a personal computer or the like, phase control data is transmitted from a CPU, and then the CPU receives video detection data detected from an image sampled and displayed at a set phase value. This processing is repeated while the value is varied to determine an optimal phase value based on the received video detection data. A method of determining an optimal phase value may integrate luminance difference values between adjacent pixels for one screen, and utilize the integrated value. Any of conventional methods requires a wait time which is the sum of a period taken for transmitting phase setting data and a period taken for measuring one screen of image sampled at a set phase value. Generally, the vertical synchronization signal is used as an interrupt signal, and the wait time extends over two interrupts, so that a problem arises in that a lot of time is taken until the automatic adjustment is completed.